1. Field of the Invention
The present invention relates to the field of power semiconductor devices. More particularly, the present invention relates to a semiconductor device employing double-diffused metal oxide semiconductor (DMOS) type technology used to construct field effect transistor (FET) devices. Moreover, the present invention relates to a structure which uses trench DMOS-FET technology to implement such devices. Still more particularly, the present invention provides for a redesigned gate signal bus, where MOS trenches are arranged in parallel formation to effect an electric field coupling between the trenches, resulting in a reduction of the peak electric field in the area around the gate signal bus.
2. Description of the Prior Art
MOS devices, particularly MOS field effect transistors (MOSFETs), represent a fundamental component of any contemporary electronic system. MOSFETs are distinguished from power MOSFETs in that power MOSFETs can dissipate more than 0.5 W and are physically larger than typical MOSFETs. Those power MOSFETs having a drain-to-source voltage of less than 150V are generally identified as low-voltage power MOSFETs and are typically used in xe2x80x9cpower managementxe2x80x9d applications. Such applications include, but are not limited to, power switches, switching regulators, and linear regulators. It is this type of power MOSFET that is the focus of the present invention.
One type of power MOSFET is a double-diffused type FET sometimes called a DMOS transistor. DMOS transistor fabrication uses diffusion to form the transistor channel regions. A power MOSFET is essentially a large array of unit-cell DMOS transistors with several additional elements to evenly distribute gating signals and control device breakdown voltage. DMOS devices have the advantage of providing low-power dissipation and high-speed capability. Accordingly, DMOS technology is preferred in high-voltage circuitry of today""s high-power integrated circuit applications. Applications in which such power MOSFETs utilizing DMOS technology are found range from high-voltage telecommunication circuits down to 3.3 volt DC-DC converters used on personal computers. Devices utilizing DMOS technology have been common throughout these applications for nearly 20 years. Many advances in DMOS technology regarding the device fabrication and device characteristics have also occurred during this period. Currently, power MOSFETs represent the third fastest growing market in the world. Performance gains are achieved by cell-density increases, which mean decreasing unit cell dimensions. Because the market for power MOSFETs is high volume and price-competitive, a premium is placed on manufacturing innovation leading to stable, low cost, and high-yielding production processes.
In the field of power MOSFET production, there have been a variety of other processes utilized. For production of the dominant device structure for DMOS power MOSFETs, there has existed the so-called xe2x80x9cplanar processxe2x80x9d of production. The planar process derives its name from the fact that the MOSFET channel and gating structures are coplanar with the silicon wafer surface. In FIG. 1, a prior art DMOS structure is shown in the form of a planar DMOS structure 10 produced by the planar process. This planar structure is predominant in mainstream production of DMOS power MOSFETs. In FIG. 1, the DMOS structure 10 includes a channel 12 and a gating structure 13. Both the channel 12 and gating structure 13 are coplanar to a silicon-wafer surface 11. Although the planar process has been well refined over the years, it exhibits considerable scaling limitations. Such limitations are becoming particularly apparent when the planar process is scaled to small-cell dimensions. As performance gains in power MOSFETs are obtained by increasing cell densityxe2x80x94and thus decreasing unit-cell dimensionsxe2x80x94the limitations in the planar process approach for such planar DMOS devices appear far sooner than the equipment""s photo lithographic limitations. This problem stems from the polysilicon gate that is used to control the power MOSFET""s channel characteristics. Basically, the gate dimension for a given junction depth cannot be reduced indefinitely without forcing the so-called JFET resistance term to become a dominating constituent of the device""s overall ON-state resistancexe2x80x94a key parameter. The JFET resistance term gains its name from an inherent, parasitic junction field effect transistor (JFET) operation that arises from the nature of the structural junctions between the layers.
Concurrent with the development of the prior art planar process described above, other technology has been developed with the goal of keeping the JFET resistance term from becoming a dominating constituent. More particularly, an emerging technology in power MOSFET production avoids the JFET problem by forming the device""s channel along the sidewalls of an etched trench. This alternative prior art design is shown in FIG. 2 and includes a trench DMOS structure 20. The trench DMOS structure 20 includes a gate channel 22 along the sidewalls 25 of a trench 24 beside gate 23. This trench 24 is etched into the silicon wafer surface 21 so that the channel 22 is positioned perpendicular to the silicon wafer surface 21. This type of production process is appropriately named xe2x80x9ctrench DMOS technology,xe2x80x9d or simply xe2x80x9ctrench technology.xe2x80x9d A benefit of this trench technology is that it virtually eliminates the JFET problem. It permits increases in cell density by orders of magnitude, the only limitation then being that imposed by the fabrication equipment.
In typical power MOSFET structures, the width of the depletion region determines the electric field that exists across the region and hence the voltage drop. Therefore, any applied voltage beyond this magnitude must be partially dropped across the thin gate oxide layer. If this becomes too great, hot electron generation can occur, which can lead to an irreversible device breakdown. Typically, this is alleviated by placing a thick layer (e.g., 8500 xc3x85) of thermally grown silicon dioxide underneath the polysilicon gate. This additional oxide layer is not inconsequential. It effectively represents one to three additional photomasking steps and a relatively long thermal cycle for its growth. In some cases, a thermal cycle upwards of nine hours is needed. Further, this additional oxide layer is commonly found to be a significant source of ionic contaminants. Such contamination can ultimately adversely influence the given device""s reliability. The use of trench technology in the power MOSFET structure of the present invention eliminates the need for this additional oxide layer.
Trench technology has not heretofore been utilized to its fullest extent. One area in which trench technology has not been utilized is in power MOSFET bus architecture. Contemporary production power MOSFETs, using trenchxe2x80x94or otherxe2x80x94technology, require a thick field oxide layer beneath the polysilicon gate bus structure to suppress hot electron injection. Another method to address this problem includes forming impurity junctions within the gate bus. That method would also suggest a field-coupling mechanism. This, however, requires more area for the gate bus since holes must be etched into the polysilicon bus to allow implanted ions into the silicon surface below. Furthermore, these junctions would be electrically floating and, hence, would not have a well-defined potential voltage. This can lead to dynamic performance degradation since bulk carriers near the junction can be modulated under certain bias conditions.
Accordingly, the prior art fails to provide any MOSFET bus architecture capable of efficient utilization of trench technology. Therefore, what is needed is a method of MOSFET device production that utilizes trench technology to redesign an element of that devicexe2x80x94namely, the gate signal bus. What is needed is such MOSFET device production that results in the formation of a value supported by the underlying epitaxial layer. Further, what is needed is such a method that ensures a production process that is shortened and thus less costly. It is the capability to fabricate efficiently an effective bus architecture that would make the use of trench technology desirable.
It is an object of the present invention to provide a power MOSFET bus architecture made with trench technology. Another object of the present invention is to provide a process for producing such a bus architecture. Yet another object of the present invention is to provide such a bus architecture with MOS trenches having enhanced depletion region widths. Still another object of the present invention is to provide a bus device capable of withstanding voltages up the maximum value supported by the epitaxial layer underlying the bus device. It is also an object of the present invention to provide such a bus device that is more quickly and cost-effectively produced than the comparable prior art devices utilizing trench technology.
The present invention focuses on using trench technology to redesign a gate signal bus of a power MOSFET device. The innovation in bus architecture is accomplished by using MOS trenches placed in such a way so as to couple the depletion region widths of the trenches to one another. Such placement thus forms a structure capable of withstanding voltages up to the maximum value supported by the underlying epitaxial layer. The generation of the depletion layer, characteristic of all MOS structures, is critical to the success of this approach of the present invention. The nature of each depletion region and thus the means of coupling of depletion region widths together in the present invention depends on both the applied voltage across the MOS system and the semiconductor dopant concentration. These factors are determined by the specifications demanded by the device using that MOS system. The spacing between the trenches is a key factor in depletion region width coupling. Accordingly, the spacing of trenches will be influences by the demands of the final device.
The trench process utilized in the present invention results in a reduction in the number of masks required to produce a power MOSFET device. Present techniques commonly require up to nine (photo) masking steps to fabricate a device. The present invention reduces the required masking steps by one. It also removes a relatively long thermal oxide formation process.
A distinguishing feature of this type of xe2x80x9creduced-maskxe2x80x9d device is the current-conduction-path. Rather than being lateral as in conventional planar MOS devices, the current-conduction-paths in MOS devices of the present invention are vertical pathsxe2x80x94through the epitaxial layer and the substrate. Further, in the present invention, the channel junctions are self-aligned to the polysilicon and trenches. Initial simulations and experimentation provided suitable results via trench dimensions of two microns of depth by one micron of width. Initial simulations were performed with the MEDICI 2 dimensional device simulator and prototyped in an edge-termination structure. The field coupling effect that allows the reduced mask to occur is a result of the two-dimensional behavior of trench technology. Because silicon trench etching can be controlled quite easily in production, the present invention is a valuable approach for power MOSFET bus device production.
Enhanced voltage protection occurs in the present invention through the coupling of the depletion regions of each trench that forms the gate bus. Within a given gate bus, there will be multiple trenches formed below a single polysilicon surface structure. Each trench contributes a depletion region within each space ofxe2x80x94epitaxy substrate material between adjacent gate trenches, so as to create an expanded depletion region. The resultant increase in the collective depletion region provides the gate bus with the ability to support an increased voltage during normal operation conditions. Such enhanced overvoltage protection is accomplished via the structural arrangement of the trenches and is easily controlled by determination of spacing for any given application.
It is to be understood that other objects and advantages of the present invention will be made apparent by the following descriptions of the drawings according to the present invention. While a preferred embodiment is disclosed, this is not intended to be limiting. Rather, the general principles set forth herein are considered to be merely illustrative of the scope of the present invention and it is to be further understood that numerous changes may be made without straying from the scope of the present invention.